This invention relates to techniques for simulating digital systems. The invention is particularly, although not exclusively, concerned with simulating the design of computer hardware, but could also be used in simulating other systems, such as complex software systems.
Design languages are known which allow the design of a digital system to be specified in terms of a number of functional units which communicate with each other by means of signals. One such language is VHDL [ANSI/IEEE Standard 1076].
Using such a language, functional units may be specified at different levels of complexity. Typically, each functional unit is initially specified at a high level, in very abstract terms, and then, as the design develops, is defined at increasingly detailed levels. It frequently turns out that the design of different units progresses at different rates: for example, in the design of a computer, the task of designing an I/O unit may be easier than that of designing the CPU or Store units, and so a lower level model of the I/O unit may become available before the equivalent models for the other units. The problem then arises of how to run the simulation model with different units at different levels.
One way of solving this problem is to use translators, for translating signals between different levels. For example, if the design consists of unit A at level 1 and unit B at level 2, then a translator could be used to translate the output signals from unit A to level 2 so that it may communicate with unit B. However, a problem with this is that such translators have to be hand-written, and require a substantial amount of effort to write and to validate. Indeed, the effort required to write and validate a translator is often greater than that for the unit itself.
The object of the present invention is to provide a way of allowing mixed-level modelling which overcomes these problems.